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clock generator for intel ? alviso chipset cy28442-2 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-07691 rev. *b revised august 3, 2005 features ? compliant to intel ? ck410m ? supports intel pentium-m cpu ? selectable cpu frequencies ? differential cpu clock pairs ? 100-mhz differential src clocks ? 96-mhz differential dot clock ? 48-mhz usb clocks ? src clocks independently stoppable through clkreq#[a:b] ? 96-/100-mhz spreadable differential clock. ? 33-mhz pci clock ? low-voltage frequency select input ?i 2 c support with readback capabilities ? ideal lexmark spread spectrum profile for maximum electromagnetic interference (emi) reduction ? 3.3v power supply ? 56-pin tssop package cpu src pci ref dot96 usb_48 x2 / x3 x5/6 x 6 x 2 x 2 x 1 block diagram pin configuration usb iref vdd_cpu ref vdd_ref cput_itp/srct7 cpuc_itp/srcc7 vdd_cpu vdd_48mhz 96_100_ssct 96_100_sscc dot96t dot96c vdd_48mhz vdd_48 divider divider divider 14.318mhz crystal pll1 cpu pll2 96mss pll3 fixed i2c logic pll reference xin xout pci_stp# fs_[c:a] vttpwr_gd#/pd sdata sclk cput cpuc srct[1:5] cpuc[1:5] vdd_src pci vdd_pci pcif vdd_pci cpu_stp# clkreq[a:b]# pci2/sel_clkreq** **96_100_sel/pcif1 cy28442-2 56 pin tssop/ssop 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 vss_ref vdd_ref pci3 pci4 pci5 vss_pci vdd_pci itp_en/pcif0 vdd_48 fs_a/48m_0 vss_48 dot96t dot96c fs_b/testmode 96_100_ssct 96_100_sscc srct1 srcc1 vdd_src srct2 srcc2 srct3 srcc3 srct4_sata srcc4_sata vdd_src vttpwrgd#/pd 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 pci_stp# cpu_stp# fs_c(test_sel)/ref0 ref1 vssa2 xin vdda2 xout sclk vss_cpu cput0 cpuc0 vdd_cpu cput1 cpuc1 iref vssa vdda cpu2t_itp/srct7 cpu2c_itp/srcc7 vdd_src_itp clkreqa#/srct6 clkreqb#/srcc6 srct5 srcc5 vss_src sdata
cy28442-2 document #: 38-07691 rev. *b page 2 of 21 pin definitions pin no. name type description 1vdd_refpwr 3.3v power supply for output 2 vss_ref gnd ground for outputs . 33,32 clkreqa#/srct6, clkreqb#,srcc6 i/o, pu 3.3v lvttl input for enabling assigned src clock (active low) or 100-mhz serial reference clock. selectable through clkreqa# defaults to enable/disable srct/c4, clkreqb# defaults to enable/disable srct/c5. assignment can be changed via smbus register byte 8. 7vdd_pci pwr 3.3v power supply for outputs . 6 vss_pci gnd ground for outputs . 3,4,5 pci o, se 33-mhz clock 8 itp_en/pcif0 i/o, se 3.3v lvttl input to enable src7 or cpu2_itp/33-mhz clock output. (sampled on the vtt_pwrgd# assertion). 1 = cpu2_itp, 0 = src7 9 pcif1/96_100_sel i/o, pd,se 33-mhz clock / 3.3v-tolerant input for 96_100m frequency selection (sampled on the vtt_pwrgd# assertion). 1 = 100 mhz, 0 = 96 mhz 10 vtt_pwrgd#/pd i, pu 3.3v lvttl input. this pin is a level sensitive strobe used to latch the fs_a, fs_b, fs_c and itp_en, 96mss_ src_sel inputs, sel_clkreq . after vtt_pwrgd# (active low) assertion, this pin becomes a real-time input for asserting power-down (active high). 11 vdd_48 pwr 3.3v power supply for outputs . 12 fs_a/48_m0 i/o 3.3v-tolerant input for cpu frequency selection/fixed 48-mhz clock output . refer to dc electrical specifications table for vil_fs and vih_fs specifications. 13 vss_48 gnd ground for outputs . 14,15 dot96t, dot96c o, dif fixed 96-mhz clock output . 16 fs_b/test_mode i 3.3v-tolerant input for cpu frequency selection . selects ref/n or tri-state when in test mode 0 = tri-state, 1 = ref/n refer to dc electrical specifications table for vil_fs and vih_fs specifications. 17,18 96_100_ssc o,dif differential 96-/100-mhz ss clock for flat-panel display 19,20,22,23, 24,25,30,31 srct/c o, dif 100-mhz differential serial reference clocks . 21,28 vdd_src pwr 3.3v power supply for outputs . 34 vdd_src_itp pwr 3.3v power supply for outputs . 26,27 src4_satat, src4_satac o, dif differential serial reference clock . recommended output for sata. 29 vss_src gnd ground for outputs . 36,35 cput2_itp/srct7, cpuc2_itp/srcc7 o, dif selectable differential cpu or src clock output . itp_en = 0 @ vtt_pwrg d# assertion = src7 itp_en = 1 @ vtt_pwrg d# assertion = cpu2 37 vdda pwr 3.3v power supply for pll . 38 vssa gnd ground for pll . 39 iref i a precision resistor is attached to this pin , which is connected to the internal current reference. 42 vdd_cpu pwr 3.3v power supply for outputs . 44,43,41,40 cput/c o, dif differential cpu clock outputs . 45 vss_cpu gnd ground for outputs . 46 sclk i smbus-compatible sclock . 47 sdata i/o smbus-compatible sdata .
cy28442-2 document #: 38-07691 rev. *b page 3 of 21 frequency select pins (fs_a, fs_b, and fs_c) host clock frequency selection is achieved by applying the appropriate logic levels to fs_a, fs_b, fs_c inputs prior to vtt_pwrgd# assertion (as seen by the clock synthesizer). upon vtt_pwrgd# being sampled low by the clock chip (indicating processor vtt voltage is stable), the clock chip samples the fs_a, fs_b, and fs_c input values. for all logic levels of fs_a, fs_b, and fs_c, vtt_pwrgd# employs a one-shot functionality in that once a valid low on vtt_pwrgd# has been sampled, all further vtt_pwrgd#, fs_a, fs_b, and fs_c transitions will be ignored, except in test mode. serial data interface to enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. through the serial data interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. the registers associated with the serial data interface initialize to their default setting upon power-up, and therefore use of this interface is optional. clock device register changes are normally made upon system initialization, if any are required. the inte rface cannot be used during system operation for power management functions. data protocol the clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. for block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to st op after any complete byte has been transferred. for byte writ e and byte read operations, the system controller can access indi vidually indexed bytes. the offset of the indexed byte is encoded in the command code, as described in table 2 . the block write and block read protocol is outlined in table 3 while table 4 outlines the correspondi ng byte write and byte read protocol. the slave receiver address is 11010010 (d2h). 48 vdda2 pwr 3.3v power supply for pll2 49 xout o, se 14.318-mhz crystal output . 50 xin i 14.318-mhz crystal input . 51 vssa2 gnd ground for pll2 . 52 ref1 o fixed 14.318 mhz clock output . 53 fs_c_test_sel/ ref0 i/o 3.3v-tolerant input for cpu frequency selection/fixed 14.318 clock output . selects test mode if pulled to greater than 1.8v when vtt_pwrgd# is asserted low. refer to dc electrical specifications table for v il_fs ,v ih_fs specifications. 54 cpu_stp# i, pu 3.3v lvttl input for cpu_stp# active low . 55 pci_stp# i, pu 3.3v lvttl input for pci_stp# active low . 56 pci2/sel_clkreq i/o, pd 3.3v-tolerant input for clkreq pin selection/fixed 33-mhz clock output . (sampled on the vtt_pwrgd# assertion). 1= pins 32,33 function as clk request pi ns, 0= pins 32,33 function as src outputs. pin definitions (continued) pin no. name type description table 1. frequency select table fs_a, fs_b, and fs_c fs_c fs_b fs_a cpu src pcif/pci ref0 dot96 usb 1 0 1 100 mhz 100 mhz 33 mhz 14.318 mhz 96 mhz 48 mhz 0 0 1 133 mhz 100 mhz 33 mhz 14.318 mhz 96 mhz 48 mhz 0 1 1 166 mhz 100 mhz 33 mhz 14.318 mhz 96 mhz 48 mhz 0 1 0 200 mhz 100 mhz 33 mhz 14.318 mhz 96 mhz 48 mhz table 2. command code definition bit description 7 0 = block read or block write operation, 1 = byte read or byte write operation (6:0) byte offset for byte read or byte write operation. fo r block read or block write operations, these bits should be '0000000'
cy28442-2 document #: 38-07691 rev. *b page 4 of 21 table 3. block read and block write protocol block write protocol block read protocol bit description bit description 1 start 1 start 8:2 slave address ? 7 bits 8:2 slave address ? 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code ? 8 bits 18:11 command code ? 8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 byte count ? 8 bits (skip this step if i 2 c_en bit set) 20 repeat start 28 acknowledge from slave 27:21 slave address ? 7 bits 36:29 data byte 1 ? 8 bits 28 read = 1 37 acknowledge from slave 29 acknowledge from slave 45:38 data byte 2 ? 8 bits 37:30 byte count from slave ? 8 bits 46 acknowledge from slave 38 acknowledge .... data byte /slave acknowledges 46:39 data byte 1 from slave ? 8 bits .... data byte n ? 8 bits 47 acknowledge .... acknowledge from slave 55:48 data byte 2 from slave ? 8 bits .... stop 56 acknowledge .... data bytes from slave / acknowledge .... data byte n from slave ? 8 bits .... not acknowledge .... stop table 4. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1start 1start 8:2 slave address ? 7 bits 8:2 slave address ? 7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code ? 8 bits 18:11 command code ? 8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 data byte ? 8 bits 20 repeated start 28 acknowledge from slave 27:21 slave address ? 7 bits 29 stop 28 read 29 acknowledge from slave 37:30 data from slave ? 8 bits 38 not acknowledge 39 stop
cy28442-2 document #: 38-07691 rev. *b page 5 of 21 control registers byte 0: control register 0 bit @pup name description 7 1 cput2_itp/srct7 cpuc2_itp/srcc7 cpu[t/c]2_itp/src[t/ c]7 output enable 0 = disable (tri-state), 1 = enable 6 1 src[t/c]6 src[t/c]6 output enable 0 = disable (tri-state), 1 = enable 5 1 src[t/c]5 src[t/c]5 output enable 0 = disable (tri-state), 1 = enable 4 1 src[t/c]4 src[t/c]4 output enable 0 = disable (tri-state), 1 = enable 3 1 src[t/c]3 src[t/c]3 output enable 0 = disable (tri-state), 1 = enable 2 1 src[t/c]2 src[t/c]2 output enable 0 = disable (tri-state), 1 = enable 1 1 src[t/c]1 src[t/c]1 output enable 0 = disable (tri-state), 1 = enable 0 1 reserved reserved byte 1: control register 1 bit @pup name description 7 1 pcif0 pcif0 output enable 0 = disabled, 1 = enabled 6 1 dot_96t/c dot_96 mhz output enable 0 = disable (tri-state), 1 = enabled 5 1 usb_48 usb_48 mhz output enable 0 = disabled, 1 = enabled 4 1 ref0 ref0 output enable 0 = disabled, 1 = enabled 3 1 ref1 ref1 output enable 0 = disabled, 1 = enabled 2 1 cpu[t/c]1 cpu[t/c]1 output enable 0 = disable (tri-state), 1 = enabled 1 1 cpu[t/c]0 cpu[t/c]0 output enable 0 = disable (tri-state), 1 = enabled 0 0 cpu pll1 (cpu pll) spread spectrum enable 0 = spread off, 1 = spread on byte 2: control register 2 bit @pup name description 7 1 pci5 pci5 output enable 0 = disabled, 1 = enabled 6 1 pci4 pci4 output enable 0 = disabled, 1 = enabled 5 1 pci3 pci3 output enable 0 = disabled, 1 = enabled 4 1 pci2 pci2 output enable 0 = disabled, 1 = enabled 3 1 reserved reserved, set = 1 2 1 reserved reserved, set = 1 1 1 reserved reserved, set = 1 0 1 pcif1 pcif1 output enable 0 = disabled, 1 = enabled
cy28442-2 document #: 38-07691 rev. *b page 6 of 21 byte 3: control register 3 bit @pup name description 7 0 src7 allow control of src[t/c]7 with assertion of pci_st p# or sw pci_stp# 0 = free running, 1 = stopped with pci_stp# 6 0 src6 allow control of src[t/c]6 with assertion of pci_st p# or sw pci_stp# 0 = free running, 1 = stopped with pci_stp# 5 0 src5 allow control of src[t/c]5 with assertion of pci_st p# or sw pci_stp# 0 = free running, 1 = stopped with pci_stp# 4 0 src4 allow control of src[t/c]4 with assertion of pci_st p# or sw pci_stp# 0 = free running, 1 = stopped with pci_stp# 3 0 src3 allow control of src[t/c]3 with assertion of pci_st p# or sw pci_stp# 0 = free running, 1 = stopped with pci_stp# 2 0 src2 allow control of src[t/c]2 with assertion of pci_st p# or sw pci_stp# 0 = free running, 1 = stopped with pci_stp# 1 0 src1 allow control of src[t/c]1 with assertion of pci_st p# or sw pci_stp# 0 = free running, 1 = stopped with pci_stp# 0 0 reserved reserved byte 4: control register 4 bit @pup name description 7 0 96_100_ssc 96_100_ssc drive mode 0 = driven in pwrdwn, 1 = tri-state 6 0 dot96t/c dot_pwrdwn drive mode 0 = driven in pwrdwn, 1 = tri-state 5 0 reserved reserved 4 0 pcif1 allow control of pcif1 with assertion of sw and hw pci_stp# 0 = free running, 1 = stopped with pci_stp# 3 0 pcif0 allow control of pcif0 with assertion of sw and hw pci_stp# 0 = free running, 1 = stopped with pci_stp# 2 1 cpu[t/c]2 allow control of cpu[ t/c]2 with assert ion of cpu_stp# 0 = free running, 1 = stopped with cpu_stp# 1 1 cpu[t/c]1 allow control of cpu[ t/c]1 with assert ion of cpu_stp# 0 = free running, 1 = stopped with cpu_stp# 0 1 cpu[t/c]0 allow control of cpu[ t/c]0 with assert ion of cpu_stp# 0 = free running, 1 = stopped with cpu_stp# byte 5: control register 5 bit @pup name description 7 0 src[t/c] src[t/ c] stop drive mode 0 = driven when pci_stp# asserted,1 = tri-state when pci_stp# asserted 6 0 cpu[t/c]2 cpu[t/c]2 stop drive mode 0 = driven when cpu_stp# asserted,1 = tri-state when cpu_stp# asserted 5 0 cpu[t/c]1 cpu[t/c]1 stop drive mode 0 = driven when cpu_stp# asserted,1 = tri-state when cpu_stp# asserted 4 0 cpu[t/c]0 cpu[t/c]0 stop drive mode 0 = driven when cpu_stp# asserted,1 = tri-state when cpu_stp# asserted 3 0 src[t/c][7:1] src[t/ c] pwrdwn drive mode 0 = driven when pd asserted,1 = tri-state when pd asserted 2 0 cpu[t/c]2 cpu[t/c]2 pwrdwn drive mode 0 = driven when pd asserted,1 = tri-state when pd asserted 1 0 cpu[t/c]1 cpu[t/c]1 pwrdwn drive mode 0 = driven when pd asserted,1 = tri-state when pd asserted
cy28442-2 document #: 38-07691 rev. *b page 7 of 21 0 0 cpu[t/c]0 cpu[t/c]0 pwrdwn drive mode 0 = driven when pd asserted,1 = tri-state when pd asserted byte 6: control register 6 bit @pup name description 7 0 test_sel ref/n or tri-state select 0 = tri-state, 1 = ref/n clock 6 0 test_mode test clo ck mode entry control 0 = normal operation, 1 = ref/n or tri-state mode, 5 0 reserved reserved 4 1 ref ref output drive strength 0 = low, 1 = high 3 1 pci, pcif and src clock outputs except those set to free running sw pci_stp function 0=sw pci_stp assert, 1= sw pci_stp deassert when this bit is set to 0, all stop pable pci, pcif and src outputs will be stopped in a synchronous manner with no short pulses. when this bit is set to 1, all sto pped pci, pcif and src outputs will resume in a synchronous manner with no short pulses. 2 hw fs_c fs_c reflects the value of the fs_c pin sampled on power-up 0 = fs_c was low during vtt_pwrgd# assertion 1 hw fs_b fs_b reflects the value of the fs_b pin sampled on power-up 0 = fs_b was low during vtt_pwrgd# assertion 0 hw fs_a fs_a reflects the value of the fs_a pin sampled on power-up 0 = fs_a was low during vtt_pwrgd# assertion byte 7: vendor id bit @pup name description 7 0 revision code bit 3 revision code bit 3 6 0 revision code bit 2 revision code bit 2 5 0 revision code bit 1 revision code bit 1 4 0 revision code bit 0 revision code bit 0 3 1 vendor id bit 3 vendor id bit 3 2 0 vendor id bit 2 vendor id bit 2 1 0 vendor id bit 1 vendor id bit 1 0 0 vendor id bit 0 vendor id bit 0 byte 8: control register 8 bit @pup name description 7 0 clkreq#b src[t/c]7clkreq#b control 1 = src[t/c]7 stoppable by clkreq#b pin 0 = src[t/c]7 not controlled by clkreq#b pin 6 1 clkreq#b src[t/c] 5 clkreq#b control 1 = src[t/c]5 stoppable by clkreq#b pin 0 = src[t/c]5 not controlled by clkreq#b pin 5 0 clkreq#b src[t/c] 3 clkreq#b control 1 = src[t/c]3 stoppable by clkreq#b pin 0 = src[t/c]3 not controlled by clkreq#b pin 4 0 clkreq#b src[t/c] 1 clkreq#b control 1 = src[t/c]1 stoppable by clkreq#b pin 0 = src[t/c]1 not controlled by clkreq#b pin 3 0 reserved reserved 2 1 clkreq#a src[t/c] 4 clkreq#a control 1 = src[t/c]4 stoppable by clkreq#a pin 0 = src[t/c]4 not controlled by clkreq#a pin byte 5: control register 5 (continued) bit @pup name description
cy28442-2 document #: 38-07691 rev. *b page 8 of 21 1 0 clkreq#a src[t/c] 2 clkreq#a control 1 = src[t/c]2 stoppable by clkreq#a pin 0 = src[t/c]2 not controlled by clkreq#a pin 0 0 reserved reserved byte 9: control register 9 bit @pup name description 7 0 s3 96_100_ssc spread spectrum selection table: s[3:0] ss% ?0000? = ?0.8%(default value) ?0001? = ?1.0% ?0010? = ?1.25% ?0011? = ?1.5% ?0100? = ?1.75% ?0101? = ?2.0% ?0110? = ?2.5% ?0111? = ?0.5% ?1000? = 0.25% ?1001? = 0.4% ?1010? = 0.5% ?1011? = 0.6% ?1100? = 0.8% ?1101? = 1.0% ?1110? = 1.25% ?1111? = 1.5% 60s2 50s1 40s0 3 1 96_100 sel software select 96_100_ssc ou tput frequency, 0 = 96 mhz, 1 = 100 mhz. 2 1 96_100 enable 96_100_ssc enable, 0 = disable, 1 = enable. 1 1 96_100 ss enable 96_100_ssc spread spectrum enable. 0 = disable, 1 = enable. 0 0 96_100 sw hw select output frequency of 96_100_ssc via software or hardware 0 = hardware, 1 = software. byte 10: control register 10 bit @pup name description 7 0 reserved reserved 6 0 clkreq#b src[t/c] 4 clkreq#b control 1 = src[t/c]4 stoppable by clkreq#b pin 0 = src[t/c]4not contro lled by clkreq#b pin 5 0 clkreq#b src[t/c] 2 clkreq#b control 1 = src[t/c]2 stoppable by clkreq#b pin 0 = src[t/c]2 not controlled by clkreq#b pin 4 0 reserved reserved 3 0 clkreq#a src[t/c]7clkreq#a control 1 = src[t/c]7 stoppable by clkreq#a pin 0 = src[t/c]7 not controlled by clkreq#a pin 2 0 clkreq#a src[t/c] 5 clkreq#a control 1 = src[t/c]5 stoppable by clkreq#a pin 0 = src[t/c]5 not controlled by clkreq#a pin 1 0 clkreq#a src[t/c] 3 clkreq#a control 1 = src[t/c]3 stoppable by clkreq#a pin 0 = src[t/c]3 not controlled by clkreq#a pin 0 0 clkreq#a src[t/c] 1 clkreq#a control 1 = src[t/c]1 stoppable by clkreq#a pin 0 = src[t/c]1 not controlled by clkreq#a pin byte 8: control register 8 (continued) bit @pup name description
cy28442-2 document #: 38-07691 rev. *b page 9 of 21 the cy28442-2 requires a parallel resonance crystal. substituting a series resonance crystal will cause the cy28442-2 to operate at the wrong frequency and violate the ppm specification. for most ap plications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. crystal loading crystal loading plays a critical role in achieving low ppm perfor- mance. to realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appro- priate capacitive loading (cl). figure 1 shows a typical crystal configuration using the two trim capacitors. an important clarification for the following discussion is that the trim capa citors are in series with the crystal not parallel. it?s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. this is not true. calculating load capacitors in addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal load ing. as mentioned previously, the capacitance on each side of the crystal is in series with the crystal. this means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (cl). while the capacitance on each side of the crystal is in series with the crystal, trim capacitors (ce1,ce2) should be calculated to provide equal capacitive loading on both sides. . as mentioned previously, the capacitance on each side of the crystal is in series with the crystal. this mean the total capac- itance on each side of the cryst al must be twice the specified load capacitance (cl). while the capacitance on each side of the crystal is in series with the crystal, trim capacitors (ce1,ce2) should be calculated to provide equal capacitance loading on both sides. use the following formulas to calculate the trim capacitor values for ce1 and ce2. cl ........................................... .........crystal load capacitance cle ............. .............. .............. actual loading seen by crystal using standard value trim capacitors ce ..................................................... external trim capacitors cs ........................................ ......stray capaci tance (terraced) ci .......................................................... internal capacitance (lead frame, bond wires etc.) clk_req[0:1]# description the clkreq#[a:b] signals are active low inputs used for clean enabling and disabling selected src outputs. the outputs controlled by clkreq#[a:b] are determined by the settings in register byte 8. the clkreq# signal is a de-bounced signal in that it?s state must remain unchanged during two consecutive rising edges of srcc to be recognized as a valid assertion or deassertion. (the assertion and deassertion of this signal is absolutely asynchronous). table 5. crystal recommendations frequency (fund) cut loading load cap drive (max.) shunt cap (max.) motional (max.) tolerance (max.) stability (max.) aging (max.) 14.31818 mhz at parallel 20 pf 0.1 mw 5 pf 0.016 pf 35 ppm 30 ppm 5 ppm figure 1. crystal capacitive clarification xtal ce2 ce1 cs1 cs2 x1 x2 ci1 ci2 clock chip trace 2.8pf trim 33pf pin 3 to 6p figure 2. crystal loading example load capacitance (each side) total capacitance (as seen by the crystal) ce = 2 * cl ? (cs + ci) ce1 + cs1 + ci1 1 + ce2 + cs2 + ci2 1 () 1 = cle
cy28442-2 document #: 38-07691 rev. *b page 10 of 21 clk_req[a:b]# assertion (clkreq# -> low) all differential outputs that were stopped are to resume normal operation in a glitch-free manner. the maximum latency from the assertion to active outputs is between 2 and 6 src clock periods (2 clocks are shown) with all src outputs resuming simultaneously. all stopped src outputs must be driven high within 10 ns of clkreq#[1:0] deassertion to a voltage greater than 200 mv. clk_req[a:b]# deassertion (clkreq# -> high) the impact of deasserting the cl kreq#[a:b] pins is that all src outputs that are set in t he control registers to stoppable via deassertion of clkreq#[a:b] are to be stopped after their next transition. the final stat e of all stopped dif signals is low, both srct clock and srcc clock outputs will not be driven. pd (power-down) clarification the vtt_pwrgd# /pd pin is a dual-function pin. during initial power-up, the pin functions as vtt_pwrgd#. once vtt_pwrgd# has been sampled low by the clock chip, the pin assumes pd functionality. the pd pin is an asynchronous active high input used to shut off all clocks cleanly prior to shutting off power to the devi ce. this signal is synchronized internal to the device prior to powering down the clock synthe- sizer. pd is also an asynchronous input for powering up the system. when pd is asserted high, all clocks need to be driven to a low value and held prior to turning off the vcos and the crystal oscillator. pd (power-down) assertion when pd is sampled high by two consecutive rising edges of cpuc, all single-ended outputs will be held low on their next high-to-lo w transition and differential clocks must held high or tri-stated (depending on the state of the control register drive mode bit) on the next diff clock# high-to-low transition within 4 clock periods. when the smbus pd drive mode bit corresponding to the differential (cpu, src, and dot) clock output of interest is programm ed to ?0?, the clock output are held with ?diff clock? pin driven high at 2 x iref, and ?diff clock#? tri-state. if the control register pd drive mode bit corre- sponding to the output of interest is programmed to ?1?, then both the ?diff clock? and the ?diff clock#? are tri-state. note the example below shows cput = 133 mhz and pd drive mode = ?1? for all differential outputs. this diagram and description is applicable to valid cpu frequenc ies 100, 133, 166, 200, 266, 333, and 400 mhz. in the even t that pd mode is desired as the initial power-on state, pd must be asserted high in less than 10 s after assertin g vtt_pwrgd#. figure 3. clk_req#[a:b] deassertion/assertion waveform srct(stoppable) srct(stoppable) srcc(free running) srct(free running) clkreq#x figure 4. power-down assertion timing waveform pd usb, 48mhz dot96t dot96c srct 100mhz srcc 100mhz cput, 133mhz pci, 33 mhz ref cpuc, 133mhz
cy28442-2 document #: 38-07691 rev. *b page 11 of 21 pd deassertion the power-up latency is less than 1.8 ms. this is the time from the deassertion of the pd pin or the ramping of the power supply until the time that st able clocks are output from the clock chip. all differential outputs stopped in a three-state condition resulting from power down will be driven high in less than 300 s of pd deassertion to a voltage greater than 200 mv. after the clock chip?s internal pll is powered up and locked, all outputs will be enabled within a few clock cycles of each other. below is an example showing the relationship of clocks coming up. cpu_stp# assertion the cpu_stp# signal is an active low input used for synchronous stopping and starting the cpu output clocks while the rest of the clock generator continues to function. when the cpu_stp# pin is asserted, all cpu outputs that are set with the smbus configuration to be stoppable via assertion of cpu_stp# will be stopped within two?six cpu clock periods after being sampled by two rising edges of the internal cpuc clock. the final states of the stopped cpu signals are cput = high and cpuc = low. there is no change to the output drive current values during the stopped state. the cput is driven high with a current value equal to 6 x (iref), and the cpuc signal will be tri-stated. figure 5. power-down deassertion timing waveform dot96c pd cpuc, 133mhz cput, 133mhz srcc 100mhz usb, 48mhz dot96t srct 100mhz tstable <1.8ns pci, 33mhz ref tdrive_pwrdn# <300 s, >200mv cpu_stp# cput cpuc figure 6. cpu_stp# assertion waveform
cy28442-2 document #: 38-07691 rev. *b page 12 of 21 cpu_stp# deassertion the deassertion of the cpu_stp# signal will cause all cpu outputs that were stopped to resume normal operation in a synchronous manner. synchronous manner meaning that no short or stretched clock pulses will be produce when the clock resumes. the maximum latency fr om the deassertion to active outputs is no more than two cpu clock cycles. cpu_stp# cput cpuc cput internal tdrive_cpu_stp#,10ns>200mv cpuc internal figure 7. cpu_stp# deassertion waveform dot96c dot96t cpuc(stoppable) cput(stoppable) cpuc(free running cput(free running pd 1.8ms cpu_stop# figure 8. cpu_stp#= driven, cp u_pd = driven, dot_pd = driven dot96c dot96t cpuc(stoppable) cput(stoppable) cpuc(free running) cput(free running) pd 1.8ms cpu_stop# figure 9. cpu_stp# = tri-state, cpu_ pd = tri-state, dot_pd = tri-state
cy28442-2 document #: 38-07691 rev. *b page 13 of 21 pci_stp# assertion the pci_stp# signal is an active low input used for synchronous stopping and starting the pci outputs while the rest of the clock generator co ntinues to function. the set-up time for capturing pci_stp# going low is 10 ns (t su ). (see figure 10 .) the pcif clocks will not be affected by this pin if their corresponding control bit in the smbus register is set to allow them to be free-running. pci_stp# deassertion the deassertion of the pci_stp# signal will cause all pci and stoppable pcif clocks to resume running in a synchronous manner within two pci clock periods after pci_stp# transi- tions to a high level. tsu pci_stp# pci_f pci src 100mhz figure 10. pci_stp# assertion waveform pci_stp# pci_f pci src 100mhz tsu tdrive_src figure 11. pci_stp# deassertion waveform fs_a, fs_b,fs_c vtt_pwrgd# pwrgd_vrm vdd clock gen clock state clock outputs clock vco 0.2-0.3ms delay state 0 state 2 state 3 wait for vtt_pwrgd# sample sels off off on on state 1 device is not affected, vtt_pwrgd# is ignored figure 12. vtt_pwrgd# timing diagram
cy28442-2 document #: 38-07691 rev. *b page 14 of 21 vtt_pwrgd# = low delay >0.25ms s1 power off s0 vdd_a = 2.0v sample inputs straps s2 normal operation wait for <1.8ms enable outputs s3 vtt_pwrgd# = toggle vdd_a = off figure 13. clock generator power-up/run state diagram
cy28442-2 document #: 38-07691 rev. *b page 15 of 21 absolute maximum conditions parameter description condition min. max. unit v dd core supply voltage ?0.5 4.6 v v dd_a analog supply voltage ?0.5 4.6 v v in input voltage relative to v ss ?0.5 v dd + 0.5 vdc t s temperature, storage non-functional ?65 150 c t a temperature, operating ambient functional 0 85 c t j temperature, junction functional ? 150 c ? jc dissipation, junction to case mil-std-883e method 1012.1 ? 20 c/w ? ja dissipation, junction to ambient jedec (jesd 51) ? 60 c/w esd hbm esd protection (human body model) mil-std-883, method 3015 2000 ? v ul-94 flammability rating at 1/8 in. v?0 msl moisture sensitivity level 1 multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supp ly sequencing is not required. dc electrical specifications parameter description condition min. max. unit all vdds 3.3v operating voltage 3.3 5% 3.135 3.465 v v ili2c input low voltage sdata, sclk ? 1.0 v v ihi2c input high voltage sdata, sclk 2.2 ? v v il_fs fs_[a,b] input low voltage v ss ? 0.3 0.35 v v ih_fs fs_[a,b] input high voltage 0.7 v dd + 0.5 v v ilfs_c fs_c input low voltage v ss ? 0.3 0.35 v v imfs_c fs_c input middle voltage 0.7 1.8 v v ihfs_c fs_c input high voltage 1.8 v dd + 0.5 v v il 3.3v input low voltage v ss ? 0.3 0.8 v v ih 3.3v input high voltage 2.0 v dd + 0.3 v i il input low leakage current except internal pull-up resistors, 0 < v in < v dd ?5 5 a i ih input high leakage current except internal pull-down resistors, 0 < v in < v dd ?5 a v ol 3.3v output low voltage i ol = 1 ma ? 0.4 v v oh 3.3v output high voltage i oh = ?1 ma 2.4 ? v i oz high-impedance output current ?10 10 a c in input pin capacitance 3 5 pf c out output pin capacitance 3 5 pf l in pin inductance ? 7 nh v xih xin high voltage 0.7v dd v dd v v xil xin low voltage 0 0.3v dd v i dd3.3v dynamic supply current at max. load and freq. per figure 15 ? 400 ma i pd3.3v power-down supply current pd asserted, outputs driven ? 70 ma i pd3.3v power-down supply current pd asserted, outputs tri-state ? 2 ma i tri tri-state current current in tri-state mode ? 100 ma
cy28442-2 document #: 38-07691 rev. *b page 16 of 21 ac electrical specifications parameter description condition min. max. unit crystal t dc xin duty cycle the device will operate reliably with input duty cycles up to 30/ 70 but the ref clock duty cycle will not be within specification 47.5 52.5 % t period xin period when xin is driven from an external clock source 69.841 71.0 ns t r / t f xin rise and fall times measured between 0.3v dd and 0.7v dd ?10.0ns t ccj xin cycle to cycle jitter as an average over 1- s duration ? 500 ps l acc long-term accuracy over 150 ms ? 300 ppm cpu at 0.7v t dc cput and cpuc duty cycle measured at crossing point v ox 45 55 % t period 100-mhz cput and cpuc period measured at crossing point v ox 9.997001 10.00300 ns t period 133-mhz cput and cpuc period measured at crossing point v ox 7.497751 7.502251 ns t period 166-mhz cput and cpuc period measured at crossing point v ox 5.998201 6.001801 ns t period 200-mhz cput and cpuc period measured at crossing point v ox 4.998500 5.001500 ns t periodss 100-mhz cput and cpuc period, ssc measured at crossing point v ox 9.997001 10.05327 ns t periodss 133-mhz cput and cpuc period, ssc measured at crossing point v ox 7.497751 7.539950 ns t periodss 166-mhz cput and cpuc period, ssc measured at crossing point v ox 5.998201 6.031960 ns t periodss 200-mhz cput and cpuc period, ssc measured at crossing point v ox 4.998500 5.026634 ns t periodabs 100-mhz cput and cpuc absolute period measured at crossing point v ox 9.912001 10.08800 ns t periodabs 133-mhz cput and cpuc absolute period measured at crossing point v ox 7.412751 7.587251 ns t periodabs 166-mhz cput and cpuc absolute period measured at crossing point v ox 5.913201 6.086801 ns t periodabs 200-mhz cput and cpuc absolute period measured at crossing point v ox 4.913500 5.086500 ns t periodssabs 100-mhz cput and cpuc absolute period, ssc measured at crossing point v ox 9.912001 10.13827 ns t periodssabs 133-mhz cput and cpuc absolute period, ssc measured at crossing point v ox 7.412751 7.624950 ns t periodssabs 166-mhz cput and cpuc absolute period, ssc measured at crossing point v ox 5.913201 6.116960 ns t periodssabs 200-mhz cput and cpuc absolute period, ssc measured at crossing point v ox 4.913500 5.111634 ns t ccj cput/c cycle to cycle jitter measured at crossing point v ox ?85ps t ccj2 cpu2_itp cycle to cycle jitter measured at crossing point v ox ? 125 ps t skew2 cpu2_itp to cpu0 clock skew measured at crossing point v ox ? 150 ps t r / t f cput and cpuc rise and fall time measured from v ol = 0.175 to v oh = 0.525v 175 700 ps t rfm rise/fall matching determined as a fraction of 2*(t r ? t f )/(t r + t f ) ?20% ? t r rise time variation ? 125 ps ? t f fall time variation ? 125 ps v high voltage high math averages figure 15 660 850 mv v low voltage low math averages figure 15 ?150 ? mv v ox crossing point voltage at 0.7v swing 250 550 mv
cy28442-2 document #: 38-07691 rev. *b page 17 of 21 v ovs maximum overshoot voltage ? v high + 0.3 v v uds minimum undershoot voltage ?0.3 ? v v rb ring back voltage see figure 15 . measure se ? 0.2 v src t dc srct and srcc duty cycle measured at crossing point v ox 45 55 % t period 100-mhz srct and srcc period measured at crossing point v ox 9.997001 10.00300 ns t periodss 100-mhz srct and srcc period, ssc measured at crossing point v ox 9.997001 10.05327 ns t periodabs 100-mhz srct and srcc absolute period measured at crossing point v ox 9.872001 10.12800 ns t periodssabs 100-mhz srct and srcc absolute period, ssc measured at crossing point v ox 9.872001 10.17827 ns t skew any srct/c to srct/c clock skew measured at crossing point v ox ? 100 ps t ccj srct/c cycle to cycle jitter measured at crossing point v ox ? 125 ps l acc srct/c long term accuracy measured at crossing point v ox ? 300 ppm t r / t f srct and srcc rise and fall time measured from v ol = 0.175 to v oh = 0.525v 175 700 ps t rfm rise/fall matching determined as a fraction of 2*(t r ? t f )/(t r + t f ) ?20% ? t r rise timevariation ? 125 ps ? t f fall time variation ? 125 ps v high voltage high math averages figure 15 660 850 mv v low voltage low math averages figure 15 ?150 ? mv v ox crossing point voltage at 0.7v swing 250 550 mv v ovs maximum overshoot voltage ? v high + 0.3 v v uds minimum undershoot voltage ?0.3 ? v v rb ring back voltage see figure 15. measure se ? 0.2 v pci/pcif t dc pci duty cycle measurement at 1.5v 45 55 % t period spread disabled pcif/pci period m easurement at 1.5v 29.99100 30.00900 ns t periodss spread enabled pcif/pci period, ssc measurement at 1. 5v 29.9910 30.15980 ns t periodabs spread disabled pcif/pci period m easurement at 1.5v 29.49100 30.50900 ns t periodssabs spread enabled pcif/pci period, ssc measurement at 1. 5v 29.49100 30.65980 ns t high pcif and pci high time measurement at 2.4v 12.0 ? ns t low pcif and pci low time measurement at 0.4v 12.0 ? ns t r / t f pcif/pci rising and falling edge rate m easured between 0.8v and 2.0v 1.0 4.0 v/ns t skew any pci clock to any pci clock skew measurement at 1.5v ? 500 ps t ccj pcif and pci cycle to cycle ji tter measurement at 1.5v ? 500 ps dot t dc dot96t and dot96c duty cycle measured at crossing point v ox 45 55 % t period dot96t and dot96c period measured at crossing point v ox 10.41354 10.41979 ns t periodabs dot96t and dot96c absolute period measured at crossing point v ox 10.16354 10.66979 ns t ccj dot96t/c cycle to cycle jitter measured at crossing point v ox ? 250 ps l acc dot96t/c long term accuracy measured at crossing point v ox ? 100 ppm ac electrical specifications (continued) parameter description condition min. max. unit
cy28442-2 document #: 38-07691 rev. *b page 18 of 21 test and measurement set-up for pci single-ended signals and reference the following diagram shows the single-ended pci outputs. t r / t f dot96t and dot96c rise and fall time measured from v ol = 0.175 to v oh = 0.525v 175 700 ps t rfm rise/fall matching determined as a fraction of 2*(t r ? t f )/(t r + t f ) ?20% ? t r rise time variation ? 125 ps ? t f fall time variation ? 125 ps v high voltage high math averages figure 15 660 850 mv v low voltage low math averages figure 15 ?150 ? mv v ox crossing point voltage at 0.7v swing 250 550 mv v ovs maximum overshoot voltage ? v high + 0.3 v v uds minimum undershoot voltage ?0.3 ? v v rb ring back voltage see figure 15. measure se ? 0.2 v usb t dc duty cycle measurement at 1.5v 45 55 % t period period measurement at 1.5v 20.83125 20.83542 ns t periodabs absolute period measurement at 1.5v 20.48125 21.18542 ns t high usb high time measurement at 2.4v 8.094 10.036 ns t low usb low time measurement at 0.4v 7.694 9.836 ns t r / t f rising and falling edge rate measured between 0.8v and 2.0v 1.0 2.0 v/ns t ccj cycle to cycle jitter measurement at 1.5v ? 350 ps ref t dc ref duty cycle measurement at 1.5v 45 55 % t period ref period measurement at 1.5v 69.8203 69.8622 ns t periodabs ref absolute period measurem ent at 1.5v 68.82033 70.86224 ns t r / t f ref rising and falling edge rate meas ured between 0.8v and 2.0v 1.0 4.0 v/ns t ccj ref cycle to cycle jitter measurement at 1.5v ? 1000 ps enable/disable and set-up t stable clock stabilization from power-up ? 1.8 ms t ss stopclock set-up time 10.0 ? ns t sh stopclock hold time 0 ? ns ac electrical specifications (continued) parameter description condition min. max. unit 0v 3.3v 2.4v 0.4v 1.5v tdc tf tr output under test probe load cap 30 pf figure 14. single-ended pci lumped load configuration
cy28442-2 document #: 38-07691 rev. *b page 19 of 21 the following diagram shows the test load configuration for the differential cpu and src outputs. cput cpuc 33? 33? 49.9? 49.9? measurement point 2pf 475? ir e f m easurem ent point 2pf srct srcc 100? d iffe rential dot96t dot96c 96_100sscc 96_100ssct figure 15. 0.7v differential clock load configuration 2.4v 0.4v 3.3v 0v t r t f 1.5v 3.3v si g nals t dc - - figure 16. single-ended output si gnals (for ac parameters measurement) ordering information part number package type product flow lead-free cy28442zxc-2 56-pin tssop commercial, 0 to 85 c CY28442ZXC-2T 56-pin tssop ? tape and reel commercial, 0 to 85 c
cy28442-2 document #: 38-07691 rev. *b page 20 of 21 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. intel and pentium are registered trademarks of intel corporation. all product and company names mentioned in this document are the trademarks of their respective holders. purchase of i 2 c components from cypress or one of its sublicensed as sociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided t hat the system conforms to the i 2 c standard specification as defined by philips. package diagrams seating plane 1 bsc 0-8 max. gauge plane 28 29 56 1.100[0.043] 0.051[0.002] 0.851[0.033] 0.508[0.020] 0.249[0.009] 7.950[0.313] 0.25[0.010] 6.198[0.244] 13.894[0.547] 8.255[0.325] 5.994[0.236] 0.950[0.037] 0.500[0.020] 14.097[0.555] 0.152[0.006] 0.762[0.030] dimensions in mm[inches] min. max. 0.170[0.006] 0.279[0.011] 0.20[0.008] 0.100[0.003] 0.200[0.008] reference jedec mo-153 package weight 0.42gms part # z5624 standard pkg. zz5624 lead free pkg. 56-lead thin shrunk small outline package, type ii (6 mm x 12 mm) z56 51-85060-*c
cy28442-2 document #: 38-07691 rev. *b page 21 of 21 document history page document title: cy28442-2 clock generator for intel ? alviso chipset document number: 38-07691 rev. ecn no. issue date orig. of change description of change ** 237627 see ecn rgl new data sheet *a 378059 see ecn rgl minor change: corrected typo in the label of the diagram from pll4 to pll3 *b 390510 see ecn rgl removed preliminary

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